This paper presents a new method to reduce consumption power in Flash ADC in 65nm CMOS technology. This method indicates a considerable reduction in consumption power, by removing comparators memories. The simulations used a frequency of 1 GHZ, resulting in decreased consumption power by approximately 90% for different processing corners. In addition, in this paper the proposed method was designed using interpolation technique for purpose of promoting the performance as well as decreasing the class of chip. The simulation results indicate that the consumption power for interpolation technique was decreased by approximately 5% compared to the proposed method. Also, we compare the results of the proposed technique with those of convertors frequently referred in other studies. The results show that the consumption power is considerably decreased, using the proposed technique.

This paper presents a high-speed, low-power and low area encoder for implementation of Flash ADCs. Key technique for design of this encoder is performed by convert the conventional 1-of-N thermometer code to 2-of-M codes (M = ¾ N). The proposed encoder is composed from two-stage; in the first stage, thermometer code are converted to 2-of-M codes by used 2-input AND and 4-input compound AND-OR gates. In the second stage by two ROM encoders, 2-of-M codes determine n-1 MSB bits and one LSB bit. The advantages of the proposed encoder rather than other similar works are high speed, low power consumption, low active area, and low latency with same bubble error removing capability. To demonstrate the mention specifications, 5-bit Flash ADCs with conventional and proposed encoders in their encoder blocks, are simulated at 2-GS/s and 3. 5-GS/s sampling rates in 0. 18-μ m CMOS process. Simulation results show that the ENOB of Flash ADCs with conventional and proposed encoders are equal. In this case, the proposed encoder outputs are determined almost 30-ps faster rather than the conventional encoder at 2-GS/s. Also, the power consumptions of the conventional and proposed encoders were 17. 94-mW and 11. 74-mW at 3. 5-GS/s sampling rate from a 1. 8-V supply, respectively. Corresponding, latencies of the conventional and proposed encoders were 3 and 2 clock cycles. In this case, number of TSPC D-FFs and logic gates of the proposed encoder is decreased almost 39% compared to the conventional encoder.